1. Field of Invention
The present invention relates to semiconductor memory, more particularly, to a sense amplifier control circuit in semiconductor memory which supplies a sense amplifier with two power source voltages of which levels are different each other, successively.
2. Discussion of Related Art
A sense amplifier in semiconductor memory basically amplifies the voltage difference between a pair of bit lines. The sense amplifier amplifies the voltage difference, carrying out operations of data read/write and data refresh in memory cells. Various operations of the sense amplifier are controlled by a separate circuit for controlling a sense amplifier.
FIG. 1 and FIG. 2 show sense amplifier control circuits in semiconductor memory according to a related art.
FIG. 1 is a circuit for generating a first NMOS sense amplifier enabling bar signal SAEN1B, first PMOS sense amplifier enabling bar signal SAEP1B, and second PMOS sense amplifier enabling bar signal SAEP2B in use of a sense amplifier enabling bar signal SAEB.
FIG. 2 is a circuit for generating an NMOS sense amplifier control signal SAN, first PMOS sense amplifier control signal SAP1, and second PMOS sense amplifier control signal SAP2 in use of the signals generated in FIG. 1.
Referring to FIG. 1, a delaying part 102 receives and delays a sense amplifier enabling bar signal SAEB for a time interval. A NOR gate 104 receives the sense amplifier enabling bar signal SAEB and an output of the delaying part 102. A NAND gate 108 receives an inverted signal of an output of the NOR gate 104 and the sense amplifier enabling bar signal SAEB. An inverter 110 outputs a first NMOS sense amplifier enabling bar signal SAEN1B by inverting an output of the NAND gate 108. A NOR gate 112 receives the output of the NOR gate 104 and the sense amplifier enabling bar signal SAEB. An inverter 114 outputs a first PMOS sense amplifier enabling bar signal SAEP1B by inverting an output of the NOR gate 112. Three inverters connected one another in series output a second PMOS sense amplifier enabling bar signal SAEP2B by delaying and inverting the output of the NOR gate 104.
Referring to FIG. 2, an inverter 202 inverts the second PMOS sense amplifier enabling bar signal SAEP2B. A NAND gate 204 receives a plurality of mat selection bar signals MSBm and MSBn. An inverter 206 inverts the first NMOS sense amplifier enabling bar signal SAEN1B. An inverter 208 inverts the first PMOS sense amplifier enabling bar signal SAEP1B. A NAND gate 210 receives outputs of the inverter 202 and NAND gate 204. An inverter 212 inverts an output of the NAND gate 210. A NAND gate 214 receives outputs of the NAND gate 204 and inverter 206. An inverter 216 inverts an output of the NAND gate 214.
A NAND gate 218 receives outputs of the inverters 216 and 208 respectively. A NAND gate 220 receives outputs of the inverter 212 and NAND gate 218. An inverter 224 outputs a second PMOS sense amplifier control signal SAP2 by inverting an output of the NAND gate 220. Two inverters 226 and 228 connected each other in series delays an output of the inverter 216, generating an NMOS sense amplifier control signal SAN. An inverter 230 generates a first PMOS sense amplifier control signal SAP1 by inverting an output of the NAND gate 218.
FIG. 3 shows a timing diagram of operational characteristics of a sense amplifier control circuit in semiconductor memory of a related art.
Referring to FIG. 3, when a mat selection bar signal MSB goes down high level to low, a sense amplifier enabling bar signal SAEB goes down to low level. Provided that the sense amplifier enabling bar signal SAEB goes down to low level, Both first PMOS and NMOS sense amplifier enabling bar signals SAEP1B and SAEN1B go down to low level while a second PMOS sense amplifier enabling bar signal SAEP2B still maintains high level.
After delayed time td of the delaying part 102 has elapsed, the first sense amplifier enabling bar signal SAEP1B goes up to high level again and the second PMOS sense amplifier enabling bar signal SAEP2B goes down to low level, while the first NMOS sense amplifier enabling bar signal SAEN1B maintains low level.
As the first NMOS sense amplifier enabling bar signal SAEN1B goes down to low level, an NMOS sense amplifier control signal SAN goes up to high level. While the first sense amplifier enabling bar signal SAEP1B stay at low level, a first PMOS sense amplifier control signal SAP1 keeps high level. While the second PMOS sense amplifier enabling bar signal SAEP2B stays at low level, a second PMOS sense amplifier control signal SAP2 is at high level. As shown in FIG. 3, the first and second PMOS sense amplifier control signals SAP1 and SAP2 are activated to high level in order. The activated interval of the first PMOS sense amplifier control signal SAP1 is relatively shorter than that of the second SAP2. This is because the sense amplifier is supplied with normal voltage through the second PMOS sense amplifier control signal SAP2 after the driving force of the sense amplifier has been greatly improved owing to overdriven voltage applied to the sense amplifier by the first PMOS sense amplifier control signal SAP1.
FIG. 4 shows a sense amplifier driving circuit in semiconductor memory.
Referring to FIG. 4, two NMOS transistors 402 and 404 are controlled by a first PMOS sense amplifier control signal SAP1 and a second PMOS sense amplifier control signal SAP2, respectively. Another NMOS transistor 406 is controlled by an NMOS sense amplifier control signal SAN. As the first PMOS sense amplifier control signal SAP1 is activated to high level, power source voltage VDD is carried to a sense amplifier as a PMOS sense amplifier driving voltage CSP. Then, the second PMOS sense amplifier control signal SAP2 is activated to high level. And, inner power supply voltage VDL relatively lower than VDD is carried to the sense amplifier as PMOS sense amplifier driving voltage CSP. Namely, after the sense amplifier has been overdriven by power supply voltage VDD having relatively high voltage level, the sense amplifier is driven normally by the following inner power supply voltage VDL. During this procedure, as the NMOS sense amplifier control signal SAN maintains high level, ground voltage VSS as NMOS sense amplifier driving voltage CSN is carried to the sense amplifier.
In the sense amplifier control circuit of the related art, the NMOS sense amplifier control signal SAN, first and second PMOS sense amplifier control signals SAP1 and SAP2 are generated from the first NMOS sense amplifier enabling bar signal SAEN1B, first and second PMOS sense amplifier enabling bar signals SAEP1B and SAEP2B in use of the sense amplifier enabling bar signal SAEB. Therefore, the circuit requires many logic gates as well as many signal transferring paths, thereby increasing a chip size.